Memory Storage
A memory device stores digital data in an array of memory cells. Each memory cell has a specific address which is essentially the intersection formed by a wordline and a digit line. Once an individual cell has been selected, its true and complementary data is amplified and latched onto its digit line pair by a sense amplifier. The digit line pair comprises the "digit line" coupling true data and the "digit bar line" for coupling complementary data to and from the memory cell.
During an inactive cycle of the memory device the digit lines are typically equilibrated to the same potential, typically one half of the supply potential. However during an active cycle, when the data is stored in or retrieved from a memory cell, at least one of the digit lines is pulled to the supply potential, V.sub.cc. Pull-up circuits of the related art are depicted in FIGS. 1A and 1B. The digit lines 1, having a p-channel sense amplifier 2, are pulled to the supply potential through the p-channel metal oxide semiconductor (PMOS) switching transistor 3 shown in FIG. 1A. The circuit is subject to large power consumption during the active cycle due to the large capacitance of the digit lines.
An alternate circuit implementation utilizes an n-channel metal oxide semiconductor (NMOS) switching transistors 4, see FIG. 1B. However, the incidence of soft error increases due to the voltage drop across the NMOS transistor 4. Soft error occurs at low supply potentials when the digit lines 1 are not pulled to a potential high enough to effectively couple a high potential to and from the memory cells. The PMOS transistor helps alleviate this problem. However since the PMOS transistor is fully conductive, as the supply potentials increase the current consumption increases. Thus, there is a need to minimize power consumption by reducing current while at the same time maintaining a valid high potential on the digit lines.